FSMDesigner is a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. It uses the Simple-Moore FSM model, guaranteeing efficient fast complex control circuits. It features graphical design of FSMs, support for automatic default transitions, validation of FSMs, a well-defined XML file format, generation of RTL HDL output for both Verilog and VHDL, full scriptability in Python, a modern GUI with undo and redo, simulation mode support, and table based data manipulation.
License: GNU General Public License v2
Changes:
This version improves several parts and introduces some new features. The main new features are SVG export and System Verilog Assertions (SVA) support for verification. This makes it possible, for example, to get a coverage analysis of your FSM simulation. Improvements include fixes in printing and mnenonic map generation.
